A conventional fabrication process of a thinfllm transistor array is now explained below by taking an example for a case where it is used to fabricate a liquid-crystal display device.
FIG. 7 shows a fabrication process of top-gate type polysilicon thinfilm transistor array to be incorporated in an active matrix type liquid-crystal display device. As shown in FIG. 7(a), polysilicon thinfilm 14 is disposed on transparent substrate 11 first, and said polysilicon thinfilm 14 is formed into a thinfilm transistor array.
After disposing gate-insulation layer 15 of a silicon-oxide thinfilm on polysilicon thinfilm 14, gate electrode 16 is formed on gate-insulation layer 15. A phosphor dopant is then implanted in source and drain regions of thinfilm transistor array by using an ion-implantation method wherein said dopant is implanted into polysilicon thinfilm 14 through gate-insulation layer 15 by using gate electrodes 16 as a mask. After applying a process to activate said implanted dopant, silicon-oxide inter-insulation layer 17 is then formed as shown in FIG. 7(b).
After this, contact holes 20 are provided in gate insulation layer 15 and inter-insulation layer 17 formed on said source and drain regions of thinfilm transistor, and, as shown in FIG. 7(c), display electrodes 12 made of ITO (Indium Tin Oxide) are disposed on these. The fabrication process of thinfilm transistor array is completed then by depositing data wiring 18 on these.
Succeeding to the above, problems associated with the conventional fabrication process of thinfilm transistor array shown in FIG. 7 are now explained in the following.
The first problem is a high probability of disconnections of display electrodes 12.
FIG. 8 shows an enlargement of region-A of contact hole 20 shown in FIG. 7(c), indicating an edge step of which height corresponds to the sum of the thicknesses of gate insulation layer 15 and inter-insulation layer 17.
As shown in FIG. 8, since the height of step of contact hole is 500 nm (sum of 100 nm of gate insulation layer and 400 nm of inter-insulation layer) while the thickness of ITO layer of display electrode 12 is 100 nm, the step coverage of ITO layer at the contact hole step is inadequate, increasing the probabilities of disconnections and other troubles.
In preventing the disconnections of display electrodes 12 at contact holes, the inadequate step coverage had been corrected by providing a tapered cross-section of gate insulation layer 15 and inter-insulation layer 17 obtained by applying a controlled etching process in forming contact holes 20.
The second problem relates to short-circuits between the display electrode 12 and the data wiring 18.
FIG. 9 shows a top view of thinfilm transistor array designed to be incorporated in a liquid-crystal display device shown in FIG. 7. This cross-section at A-A' line shown in FIG. 9 corresponds to the one shown in FIG. 7(c).
As seen from the data wiring 18 and display electrode 12 disposed at a close distance shown by B-B' line in FIG. 9 and the cross-section of these components at B-B' line in FIG. 4(a), no insulation layer had been provided between the data wiring 18 and the display electrode 12 of conventional thinfilm transistor array.
Therefore, the probability of short-circuits between the data wiring 18 and the display electrode 12 due to foreign particles introduced there-between during the patterning process of these should had been fairly high.
Since the probability of such short-circuits is higher for the shorter distance between the data wiring 18 and the display electrode 12, a proper distance had to be provided in order to reduce the probability of such, sacrificing the display area as a result of this.
The third problem relates to corrosion of said circuit components possible during the patterning process of these.
During the patterning process of data wiring 18 made of an aluminum layer, corrosion of the aluminum layer may take place during the photolithographic process employing a positive type photoresist since the aluminum layer and the ITO layer of display electrode 12 are disposed on a common plane.
Thus, a negative type photoresist had to be employed particularly during the patterning process of data wiring 18. As for the corrosion process of Al-ITO layer possible during said photolithographic process, the details of it are explained in Japanese Patent Application Hei-5-1111439.